This is my second build of a Z80 computer, the circuit is quite simple it just has lots of wires.
The 8 data lines are parallel between each device, ROM,RAM and I/O. The address lines are parallel across the ROM and RAM then some go off to do other functions like I/O decoding and memory decoding.
This is all inside a modern microcontroller, so the theory is pretty much the same it’s just easier with less wires! I find it quite rewarding to build circuits with this old technology because everything has to be considered, it requires lots of logic gates to do I/O decoding and one wire swapped over the whole thing will do very strange things!
As you see the blue lines are busses so they hold all the signals and are easier to see in the schematic.
Memory and I/O decoding
The Z80 uses a MREQ and IORQ line along with RD and WR to control memory and I/O devices
MREQ is Memory Request
IORQ is I/O Request
RD/WR is Read and Write (if you didn’t guess)
Along with the address lines, we need logic lines to decode these signals to connect to the CS (Chip Select) line of the device
The memory decoder in the schematic attached uses 2 logic gate chips, but there is a simpler one that uses only one chip but will select more memory devices.
The reason I went for the logic gate approach is so I could re use the unused gates elsewhere, saving another chip, and I only had 2 memory devices connected.
The above decoder is a very popular and easy to use one, the 74LS138. It’s a binary decoder which takes the address inputs and decodes to 8 individual outputs. It’s set at A13 to start because the 8KB chips only go to A12, so A0 to A12 are connected to each chip and the addresses outside this range are to select the actual chips.
The RFSH input is or now probably was used on the Z80 to refresh content of dynamic RAM, we use static RAM so we can use this output to disable all the memory when it’s in a refresh cycle (so the refresh cycle will do nothing)
Code in this project